The 11th IASTED International Conference on
Parallel and Distributed Computing and Networks
PDCN 2013

February 11 – 13, 2013
Innsbruck, Austria


Energy-efficient HPC via Application-aware Customized Fine-grain DVFS

Dr. Laura C. Carrington
University of California, USA


The energy cost of running HPC systems is growing to a point where it can exceed the cost of the original hardware purchase a few years into operation. This has driven the community to attempt to understand and minimize energy costs wherever possible. We present Green Queue, an automated framework that creates customized application-aware Dynamic Voltage-Frequency Scaling (DVFS) settings to reduce the energy required to run large scale scientific applications. Green Queue engages in a detailed analysis of the application to determine the energy-optimal DVFS settings for all of the application's computational phases. Green Queue supports making CPU clock frequency changes in response to intra-node and inter-node analysis of the application behavior. Our intra-node approach reduces CPU clock frequencies and therefore power consumption while CPUs lacks computational work due to inefficient data movement. Our inter-node approach reduces clock frequencies for MPI ranks that lack computational work. We investigated these techniques on a set of large scientific applications on 1024 cores of Gordon, an Intel Sandybridge based supercomputer at the San Diego Supercomputer Center. Our optimal intra-node technique showed an average measured energy savings of 10.6% and a maximum of 21.0% over regular application runs. Our optimal inter-node technique showed an average 17.4% and a maximum of 31.7% energy savings.

Biography of the Keynote Speaker

Keynote Speaker Portrait

Dr. Carrington is an expert in High Performance Computing. Her work has resulted in over 40 publication in HPC benchmarking, workload analysis, application performance modeling, analysis of accelerators (i.e. FPGAs and GPUs) for scientific workloads, tools in performance analysis (i.e. processor and network simulators), and energy-efficient computing. At UCSD, she is the director of the Performance, Modeling, and Characterization (PMaC) Lab. She is also the PI for Institute for Sustained Performance, Energy, and Resilience (SUPER) DoE SciDAC-3 and lead for the energy efficiency thrust for the institute as well as PI on a number other awards that support the lab. She has presented at numerous invited talks, member of various panels and committees, and an active member of DoD HPCMP Performance team involved in their annual HPC system procurement for past 10 years.